My Trip to DesignCon 2019 (Part 1)

William Mak

Thursday, February 14th, 2019

DesignCon 2019 KEMET KAIC

Last week, I attended DesignCon 2019, the 24th annual convention created by engineers, for engineers, to discuss the latest design tools, techniques, and applications.  Over 5,000 professionals attend each year with more than 190 speakers presenting about 15 different topics spread over three days. Each track consists of different lectures all taught by industry leaders on a wide range of topics from Power and Signal Integrity to the most recently added track, Machine Learning for Microelectronics. There is something for every electrical or electronics engineer.

I recently joined KEMET as an application engineer in charge of creating content and projects for the KEMET Application Intelligence Center, KAIC (pronounced keɪk or “cake” in plain English). KAIC is the new application research facility located at KEMET Global Headquarters in Fort Lauderdale, Florida. The facility is focused on creating application solutions and tutorials with KEMET components. For more information, please visit the KEMET Application Intelligence Center.

I attended DesignCon to continue my education with the latest in electronic design, in support of our mission at KAIC. I will be going over the highlights for Day One of the show here. Be on the lookout for my next post with a summary of the two remaining days.

Day 1 – Bootcamp

KAIC at KEMET DesignCon 2019

The first day of DesignCon kicked off with a bootcamp. The Power Integrity Bootcamp was hosted by Keysight Technologies. The bootcamp focused on Power Delivery Network (PDN) Design. A Power Delivery Network consists of three main parts. The first is a Voltage Regulator Module (VRM). Examples of this would be Low-Dropout regulator (LDO) or a Switching Mode Power Supply (SMPS). The network also contains the load, which is typically an active component like a processor, and any circuitry or interconnects between the VRM and the load.

The session was detailed and informative. These are my key takeaways:

  • Start with a target impedance (Z) based on the maximum allowed voltage ripple and load transient current.

Board Impedance Equation

  • Design the system with a flat impedance and stay within the target impedance range.
  • Optimize the de-coupling capacitor design by keeping only the minimum amount needed.
    • This reduces cost and increases reliability since it means there are chances of a solder joint failure.

Thanks for reading all about my first day at DesignCon. It was definitely a cool experience. It was great to get a taste of some of the latest trends in electronic design. Be sure to visit the KAIC website and check back for the summary of my final days at DesignCon!